// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  vdh_crg_reg_offset_field.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:42 Create file
// ******************************************************************************

#ifndef __VDH_CRG_REG_OFFSET_FIELD_H__
#define __VDH_CRG_REG_OFFSET_FIELD_H__

#define VDH_CRG_VDH_BPD_CLKEN_LEN     2
#define VDH_CRG_VDH_BPD_CLKEN_OFFSET  6
#define VDH_CRG_VDH_SCD_CLKEN_LEN     2
#define VDH_CRG_VDH_SCD_CLKEN_OFFSET  4
#define VDH_CRG_VDH_MFDE_CLKEN_LEN    2
#define VDH_CRG_VDH_MFDE_CLKEN_OFFSET 2
#define VDH_CRG_VDH_VDEC_CLKEN_LEN    2
#define VDH_CRG_VDH_VDEC_CLKEN_OFFSET 0

#define VDH_CRG_VDH_BPD_SRST_REQ_LEN     1
#define VDH_CRG_VDH_BPD_SRST_REQ_OFFSET  3
#define VDH_CRG_VDH_SCD_SRST_REQ_LEN     1
#define VDH_CRG_VDH_SCD_SRST_REQ_OFFSET  2
#define VDH_CRG_VDH_MFDE_SRST_REQ_LEN    1
#define VDH_CRG_VDH_MFDE_SRST_REQ_OFFSET 1
#define VDH_CRG_VDH_ALL_SRST_REQ_LEN     1
#define VDH_CRG_VDH_ALL_SRST_REQ_OFFSET  0

#define VDH_CRG_VDH_MFDE_IDLE_LEN       1
#define VDH_CRG_VDH_MFDE_IDLE_OFFSET    7
#define VDH_CRG_VDH_SCD_IDLE_LEN        1
#define VDH_CRG_VDH_SCD_IDLE_OFFSET     6
#define VDH_CRG_VDH_BPD_IDLE_LEN        1
#define VDH_CRG_VDH_BPD_IDLE_OFFSET     5
#define VDH_CRG_VDH_IDLE_LEN            1
#define VDH_CRG_VDH_IDLE_OFFSET         4
#define VDH_CRG_VDH_BPD_SRST_OK_LEN     1
#define VDH_CRG_VDH_BPD_SRST_OK_OFFSET  3
#define VDH_CRG_VDH_SCD_SRST_OK_LEN     1
#define VDH_CRG_VDH_SCD_SRST_OK_OFFSET  2
#define VDH_CRG_VDH_MFDE_SRST_OK_LEN    1
#define VDH_CRG_VDH_MFDE_SRST_OK_OFFSET 1
#define VDH_CRG_VDH_ALL_SRST_OK_LEN     1
#define VDH_CRG_VDH_ALL_SRST_OK_OFFSET  0

#define VDH_CRG_VDH_RAS_CTRL_FLAG_LEN    1
#define VDH_CRG_VDH_RAS_CTRL_FLAG_OFFSET 0

#define VDH_CRG_VDEC_RAS_ERR_INT_LEN    1
#define VDH_CRG_VDEC_RAS_ERR_INT_OFFSET 0

#define VDH_CRG_CMP_ECC_MULTI_ERR_LEN      1
#define VDH_CRG_CMP_ECC_MULTI_ERR_OFFSET   3
#define VDH_CRG_CMP_ECC_ERR_LEN            1
#define VDH_CRG_CMP_ECC_ERR_OFFSET         2
#define VDH_CRG_VCTRL_ECC_MULTI_ERR_LEN    1
#define VDH_CRG_VCTRL_ECC_MULTI_ERR_OFFSET 1
#define VDH_CRG_VCTRL_ECC_ERR_LEN          1
#define VDH_CRG_VCTRL_ECC_ERR_OFFSET       0

#define VDH_CRG_VDEC_RAS_INT_MASK_LEN    1
#define VDH_CRG_VDEC_RAS_INT_MASK_OFFSET 0

#define VDH_CRG_VDEC_RAS_ERR_INT_STATE_LEN    1
#define VDH_CRG_VDEC_RAS_ERR_INT_STATE_OFFSET 0

#endif // __VDH_CRG_REG_OFFSET_FIELD_H__
